Data transmission system

ABSTRACT

A data transmission system includes a first bus; a first bus master coupled to the first bus; a second bus master coupled to the first bus; a bus arbiter coupled to the first and second bus masters to provide an authorization of bus master operation to the first and second bus masters selectively; and a bus request holding circuit, which is coupled between the second bus master and the bus arbiter. The bus request holding circuit holds a bus request signal supplied from the second bus master for an appropriate period of time in response to a signal from the first bus master.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a data transmission system used in acomputer system.

BACKGROUND OF THE INVENTION

A conventional data bus system, such as AMBA (high performancemicro-controller bus system) provided by ARM Ltd., which includes a highperformance AHB bus and a peripheral APB bus. In this system, a highperformance device (bus master) is coupled to the high performance AHBbus. Another bus master, such as a CPU, is also coupled to the highperformance AHB bus. An AHB bus arbiter allows selectively one of thosetwo bus masters to access the high performance AHB bus.

According to the above described conventional system, however, the CPUcannot perform any operation while the other bus master, highperformance device, is accessing the high performance AHB bus. Even ifan interrupt is requested to the CPU, the interrupt operation cannot becarried out until the high performance device stops sending bus requestsignals. If the system is designed so as that bus requests are providedwith a predetermined interval, the performance of the system getslowered.

OBJECTS OF THE INVENTION

Accordingly, it is an object of the present invention to provide a datatransmission system in which data buses are efficiently controlled indata transferring operation.

Additional objects, advantages and novel features of the presentinvention will be set forth in part in the description that follows, andin part will become apparent to those skilled in the art uponexamination of the following or may be learned by practice of theinvention. The objects and advantages of the invention may be realizedand attained by means of the instrumentalities and combinationsparticularly pointed out in the appended claims.

SUMMARY OF THE INVENTION

According to the present invention, a data transmission system includesa first bus; a first bus master coupled to the first bus; a second busmaster coupled to the first bus; a bus arbiter coupled to the first andsecond bus masters to provide an authorization of bus master operationto the first and second bus masters selectively; and a bus requestholding circuit, which is coupled between the second bus master and thebus arbiter. The bus request holding circuit holds a bus request signalsupplied from the second bus master for an appropriate period of time inresponse to a signal from the first bus master.

Preferably, the bus request holding circuit performs a holding operationafter a process of the second bus master is completed, if the second busmaster is in operation when the holding operation is requested.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a data transmission system accordingto a first preferred embodiment of the present invention.

FIG. 2 is a block diagram showing a bus request holding circuit, used inthe data transmission system according to the first preferredembodiment, shown in FIG. 1.

FIG. 3 is a block diagram showing a data transmission system accordingto a second preferred embodiment of the present invention.

FIG. 4 is a block diagram showing a bus request holding circuit, used inthe data transmission system according to the second preferredembodiment, shown in FIG. 3.

DETAILED DISCLOSURE OF THE INVENTION

In the following detailed description of the preferred embodiments,reference is made to the accompanying drawings which form a part hereof,and in which is shown by way of illustration specific preferredembodiments in which the inventions may be practiced. These preferredembodiments are described in sufficient detail to enable those skilledin the art to practice the invention, and it is to be understood thatother preferred embodiments may be utilized and that logical, mechanicaland electrical changes may be made without departing from the spirit andscope of the present inventions. The following detailed description is,therefore, not to be taken in a limiting sense, and scope of the presentinventions is defined only by the appended claims.

FIG. 1 is a block diagram showing a data transmission system accordingto a first preferred embodiment of the present invention. A datatransmission system 10 includes a high performance AHB bus 100; a CPU(bus master) 105; a bus arbiter 110; a peripheral bus 120; a highperformance peripheral device (bus master) 130; a bus request holdingcircuit 140; and an interrupt controller 150.

The CPU 105 is connected through a bus interface 106 to the highperformance bus 100. The bus interface 106 is connected to the busarbiter 110. The high performance bus 100 is connected to a RAM 107; aROM 108; a bridge circuit 109; and a bus request holding circuit 140. Anoutput terminal of the bus arbiter 110 is connected through a busdecoder 111 to the RAM 107, ROM 108, a bridge circuit 109, a bus requestholding circuit 140 and the high performance peripheral device 130 via aselection line 112. The bridge circuit 109 is connected between the highperformance bus 100 and the peripheral bus 120, which is connected to atimer 121 and a UART 122. A timer 121 and a UART 122 supplies aninterrupt signal to the interrupt controller 150, which supplies aninterrupt request signal 113 to the CPU 105.

The high performance peripheral device 130 supplies a bus request inputsignal 144 to the bus request holding circuit 140, which supplies a busrequest output signal 145 to the bus arbiter 110. The bus arbiter 110supplies an acknowledge signal 102 to the high performance peripheraldevice 130.

The high performance AHB bus 100 is a main memory bus. The highperformance peripheral device 130, which transmit a large amount ofdata, and the CPU 105 are bus masters. The high performance peripheraldevice 130 sends a bus request signal 101 to the bus arbiter 110 toaccess each slave. When receiving the acknowledge signal 102 from thebus arbiter 110, the high performance peripheral device 130 is allowedto access each slave. The bus arbiter 110 controls access to a varietyof slaves via the bus decoder 111 and selection line 112.

The bus 120 operates in the same manner as the high performance bus 100.The bus 120 is connected to the other bus 100 through the bus bridgecircuit 109, which is a slave of the high performance bus 100.

The bus request holding circuit 140 is capable to hold a bus requestsignal from the high performance peripheral device 130.

FIG. 2 is a block diagram showing the bus request holding circuit 140,used in the data transmission system 10 according to the first preferredembodiment, shown in FIG. 1. The bus request holding circuit 140includes a register 141, which can be accessed by the high performancebus 100 and selection line 112; and a holding logic circuit 142, whichholds a bus request signal 144 from the high performance peripheraldevice 130.

The register 141 is set at “1” to hold the bus request signal 144, whichis set at “0” to cancel a holding condition of the bus request signal144. When “0” is set at the register 141, the holding logic circuit 142allows the bus request signal 144 to pass through to enable a busrequest signal 145. In other words, a bus request is supplied to the busarbiter 110. On the other hand, when “1” is set at the register 141, theholding logic circuit 142 disables the bus request signal 145 even ifthe bus request is provided.

The bus request holding circuit 140 performs a holding operation after aprocess of the high performance peripheral device 130 is completed, ifthe high performance peripheral device 130 is in operation when theholding operation is requested. When the register 141 has been set at“0” and the bus request signal 145 has been in enable state, the holdinglogic circuit 142 would not disable the bus request signal 145 as longas the bus request signal 144 keeps enable state “1”. In other words,the holding logic circuit 142 makes the bus request signal 145 to bedisable “0”, when the bus request signal 144 becomes disable “0” nexttime.

According to the first preferred embodiment, bus requesting can becontrolled by the CPU 105, so that the CPU 105 can have a priority ofoperation without lowering the system performance. In addition, the busrequest holding circuit 140 can wait holding of bus request until thecurrent job of the high performance peripheral device 130 is completed.As a result, it is prevented to repeat the same processing, which isinterrupted.

FIG. 3 is a block diagram showing a data transmission system accordingto a second preferred embodiment of the present invention.

FIG. 4 is a block diagram showing a bus request holding circuit, used inthe data transmission system according to the second preferredembodiment, shown in FIG. 3. In FIGS. 3 and 4, the same or correspondingelements to those in FIGS. 1 and 2 are represented by the same referencenumerals, and the same description will not be repeated to avoidredundancy.

According to the system 10, shown in FIG. 3, an interrupt controller 150is designed to supply an interrupt signal 113 to a bus request holdingcircuit 140. The bus request holding circuit 140 is operable inaccordance with a high performance bus 100 and selection line 112 andthe interrupt signal 113, supplied from the interrupt controller 150.

The bus request holding circuit 140 further includes another register146 and an interrupt detector 147. Input terminals of the register 146are connected to the bus 100 and the selection line 112. An outputterminal of the register 146 is coupled to an input terminal of theinterrupt detector 147. Another input terminal of the interrupt detector147 is connected to an interrupt controller 150 to receive the interruptsignal 113. An output terminal of the interrupt detector 147 is coupledto an input terminal of a register 141.

According to the second preferred embodiment, the bus request holdingcircuit 140 can hold a bus request signal HBURSEQIN 144 in accordancewith the interrupt signal 113, which may represent interrupt requests ofperipheral devices or external devices. The register 146 can be set at“1” or “0” in accordance with a bus 100 and selection line 112.

In operation, the register 146 is set at “1” according to a bus 100 andselection line 112 in order to set the register 141 at “1”. When aninterrupt signal 113 is detected while the register 146 is set at “1”,the interrupt detector 147 set the register 141 at “1”. In this case,the bus request holding circuit 140 operates in the same manner as thefirst preferred embodiment. On the other hand, when the register 146 isset at “0” according to bus 100 and selection line 112, the bus requestsignal HBURSEQIN 144 is not held in response to an interrupt signal 113.

As described above, according to the second preferred embodiment, thebus request signal 144 can be held in response to an interrupt signal113. As a result, disadvantages that happen when the bus request has ahigher priority than the interrupt request can be solved. And therefore,the system can be operated reliably.

The present invention is applicable to a system LSI, having a datasystem such as AMBA. A plurality of bus masters may be used in thesystem LSI in addition to a CPU. In this case, the number of registersholding bus request signals can be increased in accordance the number ofbus masters. Operation of holding a bus request signal and cancelingholding state of a bus request signal can be controlled using a terminalof a LSI, coupled to the holding logic circuit 142.

1. A data transmission system, comprising: a first bus; a first busmaster coupled to the first bus; a second bus master coupled to thefirst bus; a bus arbiter coupled to the first and second bus masters toprovide an authorization of bus master operation to the first and secondbus masters selectively; and a bus request holding circuit, which iscoupled between the second bus master and the bus arbiter, wherein thebus request holding circuit holds a bus request signal supplied from thesecond bus master for an appropriate period of time in response to asignal from the first bus master.
 2. A data transmission systemaccording to claim 1, wherein the bus request holding circuit performs aholding operation after a process of the second bus master is completed,if the second bus master is in operation when the holding operation isrequested.
 3. A data transmission system according to claim 1, whereinthe bus request holding circuit comprises a first register coupled tothe first bus and the first bus master; and a logic circuit, whichdecides holding/non-holding of the bus request signal in accordance withan output signal of the first register.
 4. A data transmission systemaccording to claim 3, wherein the bus request holding circuit furthercomprises a second register coupled to the first bus and the first busmaster; and an interrupt detector coupled to the first and secondregisters to detect an interruption request, wherein the first registeris operable in accordance with the holding request signal from the firstbus master or with an output signal of the interrupt detector.
 5. A datatransmission system according to claim 1, wherein the first bus masteris a CPU and the second bus master is a high performance peripheraldevice.
 6. A data transmission system according to claim 1, furthercomprising: a second bus; a bus bride circuit coupled to the first busand second bus; a peripheral device coupled to the second bus, whereinthe first bus is a higher performance main bus to be connected to amemory device, and the second bus is a lower performance bus.